TSMC's 1.6nm Technology Announced for Late 2026: A16 with “Super Power Rail” Backside Power

TSMC's 1.6nm Technology Announced for Late 2026: A16 with “Super Power Rail” Backside Power

With the arrival of spring comes rain, flowers and, in the technology industry, TSMC's annual technology symposium series. With customers spread across the globe, Taiwan's Pure Play Foundry has adopted an interesting strategy to update its users on its fab plans, holding a series of symposiums from Silicon Valley to Shanghai. Kicking off the series each year – and giving us our first real look at TSMC's updated foundry plans for the coming years – is the Santa Clara stop, where the company has gone from a more advanced lithography process to a larger scale. , has detailed several new wafer-to-wafer technologies. – Scalable chip packing options.

Today we're publishing several stories based on TSMC's various offerings, starting with TSMC's marquee announcement: their A16 process node. Meanwhile, for the rest of our symposium stories, please be sure to check out Related Reading below, and check back for additional stories.

Headlining its Silicon Valley stop, TSMC announced its first 'angstrom-class' process technology: the A16. Following a production schedule change that removed backside power delivery network technology (BSPDN) from TSMC's N2P node, the new 1.6nm-class production node is now the first to introduce BSPDN into TSMC's chipmaking portfolio. There will be action. With the addition of backside power capabilities and other improvements, TSMC expects the A16 to offer significantly better performance and energy efficiency than TSMC's N2P fabrication process. It will be available to TSMC's clients starting H2 2026.

TSMC A16: Combining GAAFET with Backside Power Delivery

At a high level, TSMC's A16 process technology will rely on gate-all-round (GAAFET) nanosheet transistors and have a backside power rail, which will improve power conduction and slightly increase transistor density. Compared to TSMC's N2P fabrication process, the A16 is expected to offer an 8% to 10% performance improvement at the same voltage and complexity, or a 15% to 20% reduction in power consumption at the same frequency and transistor count. TSMC isn't yet listing detailed density parameters, but the company says the chip's density will increase from 1.07x to 1.10x — keeping in mind that the transistor density is much higher than that of the transistors used. Depends on type and libraries.

A key innovation of TSMC's A16 node is its Super Power Rail (SPR) backside power delivery network, a first for TSMC. The contract chipmaker claims that the A16's SPR is specifically designed for high-performance computing products that feature both complex signal routes and dense power circuitry.

As previously reported, with this week's announcement, the A16 has now become the launch vehicle for backside power delivery at TSMC. The company was BSPDN technology was initially offered with N2P in 2026.But for reasons that aren't entirely clear, the tech has moved from N2P to A16. TSMC's official timing for N2P in 2023 was always a bit loose, so it's hard to say whether this represents too much of a practical delay for BSPDN at TSMC. But at the same time, it is important to point out that the name A16 is not just N2P, but it will be a separate technology from N2P.

TSMC isn't the only fab to pursue backside power delivery, and accordingly, we're seeing a number of variations in the technique across different fabs. The overall industry has three approaches to BSPDN: Imec's Buried Power Rail, Intel's PowerVia, and now TSMC's Super Power Rail.

The oldest technique, Imec's Buried Power Rail, essentially places the power delivery network on the backside of the wafer and then connects the logic cells' power rail to the power contact using nano TSVs. This enables some area measurements and does not add too much complexity to the output. Another implementation, Intel's PowerVia, connects the power to the contact of the cell or transistor, providing a better result, but at the cost of complexity.

Finally, we have TSMC's new Super Power Rail BSPDN technology, which connects the backside power network directly to the source and drain of each transistor. According to TSMC, it's the most efficient technology in terms of area scaling, but the tradeoff is that it's also the most complex (and expensive) when it comes to production.

That TSMC chose to go with the most complex version of BSPDN may be part of the reason we've seen it removed from N2P, as implementing it would ultimately increase both time and costs. . This leaves the A16 as TSMC's premier performance node for the 2026/2027 timeframe, while the N2P could be positioned to offer a more balanced combination of performance and cost efficiency.

The Angstrom Era begins at the end of 2026 with a new node naming convention.

Finally, as with Intel, we're also seeing TSMC adopt a new process node convention starting with this generation of technology. The name itself is largely arbitrary – and has been for many years in the fab industry – but with existing node names that are already in single digits (e.g. N2), the industry can refer to a node for something. Names need to be recalibrated. Smaller than a nanometer. And so we arrive at the 'Angstrom era'. But regardless of what exactly it's called or why it's called it, the bottom line is that the A16 will be the next-generation node beyond TSMC's 2nm-class products.

TSMC expects to begin volume production on the A16 in H2 2026, so it is likely that the first products based on this technology will hit the market in 2027. Intel's 14A; Even though 2+ years have passed and no one is producing BSPDN in volume today, there is still plenty of time to change plans and roadmaps.

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