TSMC Wants To Scale Up Chips Using Bigger Packages As Part of Its System-on-Wafer “SoW” Technology

TSMC Wants To Scale Up Chips Using Bigger Packages As Part of Its System-on-Wafer “SoW” Technology

Well, forget chip shrinkage and focus on interposer development. TSMC has implemented this by unveiling ambitious plans for the next generation of SoW packaging.

TSMC sees next-gen “SoW” chip packaging as a key factor for future growth, making chips bigger than ever before!

Before diving into what TSMC has revealed, let's talk about the interposer. Imagine a chip in your hand. Well, it's a powerful one if you assume it. Now, if you're looking to harness more capabilities from a single chip, instead of going the innovative route, the industry slaps together multiple chips and interconnects them to get the overall power. To do this, interposer or chip packaging comes in handy. In the era of AI and HPC, where computing power has become more essential than ever, chip packaging has played a significant role in driving the industry forward, and it looks set to continue.

On TSMC's Technology Symposium, where the firm showcased its A16 process and revealed many other details, the company told us what to expect with the next generation of interposers. Right now, traditional CoWoS packaging allows markets to go up to 3.3 times TSMC's reticle range. Here reticle range refers to the multiplier applied to the standard reticle size range to determine the effective usable area. Simply put, the bigger the multiplier, the better.

Moving on to the more interesting part, TSMC has revealed that its upcoming CoWoS-L packaging, which is slated to debut by 2026, plans to come with 5.5x TSMC's reticle range, which means It will include 12 HBM memory stacks. Accommodating a large substrate measuring 100×100 mm. With this innovation, the Taiwanese giant plans to squeeze out 3.5 times more computing performance than the previous generation, and this is just the beginning as the firm has big plans for the future.

By 2027, TSMC plans to introduce CoWoS with an 8x reticle range, supporting a larger 120mm x 120mm substrate, integrating four different SoICs, and setting a new tone for markets to follow. go A dedicated SoW packaging standard is also mentioned, with sixty HBM stacks reported to feature 40 times the reticle range and is clearly targeted for future data center clusters, making it The future looks really exciting and SoW, TSMC expects to achieve 40 times the performance of modern day options.

Advances in chip packaging show that process shrinkage isn't the only factor determining the future of computing power. Recent developments have already shown us that CoWoS will play a significant role in shaping the future of the AI ​​and HPC industries.

News Source: Anandtech

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