TSMC Readies Next-Gen HBM4 Base Dies, Built on 12nm and 5nm Nodes

TSMC Readies Next-Gen HBM4 Base Dies, Built on 12nm and 5nm Nodes

One of the many big changes coming with HBM4 memory is the sheer width of the immediate memory interface. With the fourth-generation memory standard moving from an already wide 1024-bit interface to an ultra-wide 2048-bit interface, the HBM4 memory stack will no longer be business as usual. Chip manufacturers will need to adopt more advanced packaging methods than those used today to accommodate larger memory.

As part of its European Technology Symposium 2024 presentation, TSMC offered some fresh details on the base dies it will develop for HBM4, which will be made using the logic process. With TSMC planning to use variants of its N12 and N5 processes for the task, the company expects to gain a favorable position in the HBM4 manufacturing process, as memory fabs are currently economically viable as such. are not equipped to generate advanced logic – if they can generate Absolutely them.

For the first wave of HBM4, TSMC is planning to use two fabrication processes: N12FFC+ and N5. While they serve the same purpose — integrating HBM4E memory with next-generation AI and HPC processors — they are used in two different ways to integrate memory for high-performance processors for AI and HPC applications. will be done

“We are working with key HBM memory partners (Micron, Samsung, SK Hynix) on advanced nodes for HBM4 full stack integration,” said senior director of design and technology platforms at TSMC. “The N12FFC+ can reach HBM for cost-effective base die performance and the N5 base die can deliver even more logic with much less power at HBM4 speeds.”

TSMC logic for HBM4 base die
N12FFC+ N5
Area 1X 0.39X
Logic GHz @ Power 1X 1.55X
Power @ GHz 1X 0.35X

TSMC's base die built on the N12FFC+ fabrication process (12nm FinFet Compact Plus, which officially belongs to 12nm-class technology, but is rooted in TSMC's well-proven 16nm FinFET production node) HBM4 silk will be used to install on the memory stack. Interposer with System on Chips (SoCs). TSMC believes their 12FFC+ process is optimized to achieve HBM4 performance, allowing memory vendors to build 12-Hi (48 GB) and 16-Hi stacks (64 GB) with bandwidth per stack. As well as more than 2 TB/sec.

“We are also optimizing CoWoS-L and CoWoS-R for HBM4,” said the senior director. “Both CoWoS-L and CoWoS-R (use) eight layers to enable routing of over 2,000 interconnected HBM4s with (adequate) signal integrity.”

The HBM4 base on the N12FFC+ will play a key role in the construction of System-in-Packages (SiPs) using TSMC's CoWoS-L or CoWoS-R advanced packaging technology, which offers interposers up to 8x reticle size – 12 HBM4 memory stacks. Plenty of room for Currently, according to TSMC data, the HBM4 can achieve a data transfer rate of 6 GT/s at a current of 14mA.

“We collaborate with EDA partners such as Cadence, Synopsys, and Ansys to verify HBM4 channel signal integrity, IR/EM, and thermal accuracy,” explained a TSMC representative.

Meanwhile, as an even more advanced alternative, memory manufacturers will also have the option to tap TSMC's N5 process to run off their HBM4 base. The N5 build base dies will pack even more logic, consume less power, and offer even greater performance. But arguably the most important benefit is that such advanced process technology will enable very small interconnect pitches on the order of 6 to 9 microns. This will allow N5 base dies to be used with direct bonding, enabling HBM4 to be 3D stacked right on top of logic chips. Direct bonding allows for even greater memory performance, which is expected to be a big boost for AI and HPC chips that are always looking for more memory bandwidth.

We already know this. TSMC and SK Hynix collaborate on HBM4 chipsets.. It is likely that TSMC will also produce the HBM4 base die for Micron. Otherwise, we'd be more surprised to see TSMC working with Samsung, as the conglomerate already has its own advanced logic fabs through its Samsung Foundry unit.

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