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TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today's

TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today's

TSMC is no stranger to making big chips. In addition to the ~800mm2 reticle range of its typical logic process, the company produces even larger chips by placing multiple dies on a single silicon interposer, using its chip-on-wafer-on-substrate (CoWoS) technology. But despite current-generation CoWoS allowing for interposers up to 3.3x TSMC's reticle range, TSMC plans to build even bigger ones in response to anticipated demand from the HPC and AI industries. To that end, as part of the company's North American Technology Symposium last week, TSMC announced that they are developing the means to make large-sized interposers that can reach 8x the range of the reticle.

TSMC's current-generation CoWoS technology allows for interposers up to 2831 mm.2 And the company is already seeing customers come up with designs that push those limits. AMD's Instinct MI300X accelerator and NVIDIA's upcoming B200 accelerator are both prime examples, as they pack larger logic chips (3D stacked in the case of AMD's products) and a total of eight HBM3/HBM3E memory stacks. are The total space provided by the interposer gives these processors great performance, but chip developers still want to go more powerful. And to get there as quickly as possible, they'll have to get bigger to include more logic chips and more memory stacks.

For their next-generation CoWoS product slated to launch in 2026, TSMC plans to release CoWoS_L, which will offer approximately 5.5 times the maximum interposer size compared to photomasks, totaling is 4719 mm². This next-generation package will support 12 HBM memory stacks and require larger substrate dimensions at 100×100 mm. Coupled with process node improvements over the next few years, and TSMC expects chips based on this generation of CoWoS to deliver 3.5x the compute performance of current generation CoWoS chips.

Further down the line, in 2027 TSMC plans to introduce a version of CoWoS that allows for interposers 8 times larger than the reticle range. This would offer a sufficient 6,864 mm² of space for a chiplet on a 120×120 mm substrate. TSMC envisions using this technology for designs that integrate four stacked system-on-integrated chips (SoICs), with 12 HBM4 memory stacks and additional I/O dies. TSMC projects that this will enable chip designers to double performance once again, producing chips that will outperform current-generation chips by 7x.

Of course, building such large chips will come with its own consequences, above and beyond what TSMC has to deal with. Enabling chip designers to build such great processors will impact system design, as well as how data centers accommodate these systems. TSMC's 100×100mm substrate will ride on the OAM 2.0 form factor range, with modules measuring 102×165mm to begin with. And if that generation of CoWoS doesn't break the current OAM form factor, 120×120mm chips certainly will. And, of course, all that extra silicon requires extra power and cooling, which is why we're already seeing hardware vendors gearing up to cool multi-kilowatt chips by investigating liquid and immersion cooling. are

Ultimately, even if Moore's Law has slowed in terms of transistor density improvements, CoWoS offers an outlet for producing chips with a larger number of transistors. So with TSMC set to offer interposers and substrates with more than twice the area of ​​today's solutions, larger chips for HPC systems will only continue to grow in both performance and size.

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