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TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While much of the focus on TSMC is aimed at its flagship nodes, such as the N3E and N2, there will continue to be loads of chips using more mature and proven process technologies for years to come. That's why TSMC continues to improve its existing nodes, including its current-generation 5nm-class offering. To that end, at its North American Technology Symposium 2024, the company introduced a new, optimized 5nm class node: the N4C.

TSMC's N4C process belongs to the company's 5nm-class family of fab nodes and is a superset of N4P, the most advanced technology in the family. In an effort to further reduce 5nm manufacturing costs, TSMC is implementing several changes for the N4C, including redesigning their standard cells and SRAM cells, changing some design principles, and increasing the number of masking layers. Involves reducing. As a result of these improvements, the company expects N4C to achieve smaller die sizes as well as a reduction in production complexity, resulting in an 8.5% reduction in die costs. Additionally, with the same wafer-level defect density rate as N4P, N4C offers even higher active yields thanks to its reduced die area.

“So, we didn't work with our 5nm and 4nm (technologies),” said Kevin Zhang, vice president of business development at TSMC. “From N5 to N4, we achieved a 4% density improvement optical shrinkage, and we continue to increase transistor efficiency. We now bring N4C to our 4 nm technology portfolio. N4C to our customers Allowing you to reduce your costs. To further reduce the overall product level cost of ownership to optimize mask and original IP designs such as standard cells and SRAM.

TSMC says the N4C may use the same design infrastructure as the N4P, although it's unclear if the N5 and N4P IP can be reused for N4C-based chips. Meanwhile, TSMC indicates that it offers a variety of options for chipmakers to find the right balance between cost benefits and design efforts, so companies interested in adopting 4nm-class process technologies should visit N4C. Can adapt well.

The N4C development comes as many of TSMC's chip design customers prepare to launch chips based on the company's latest generation of FinFET process technology, the 3nm N3 series. While the N3 is expected to be a successful family, the high costs of the N3B have been a problem, and the generation has been marked by a drop in efficiency and a drop in transistor density. As a result, the N4C could become a larger, longer-lived node at TSMC, suitable for customers who want to stick with a more cost-effective FinFET node.

“This is a very important addition, we're working with our customer, basically to get more value out of their 4 nm investment,” Zhang said.

TSMC expects to begin volume production of N4C chips sometime next year. And with TSMC developing the 5nm-class for nearly half a decade now, N4C should be able to hit the ground running in terms of volume and production.

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