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TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year

TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year

As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024. Increased transistor density on N3E along with efficiency.

N3E in production, well production

The N3E is already in volume production, with TSMC reporting that they are seeing “tremendous” production on the second-generation 3nm-class process Note. According to the company, the N3E's D0 defect density is relatively on par with the N5, matching the older node's defect rate for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing a final, ever-improved generation of FinFET technology. So for TSMC bleeding-edge customers like Apple, which just launched its M4 SoC, it's allowing them to reap the benefits of a better process node relatively quickly.

“N3E started volume production in the fourth quarter of last year, as planned,” a TSMC executive said at the event. “We've seen tremendous productivity gains on consumer products, so they went to market as planned.”

TSMC's N3E node is a relaxed version of the N3B, eliminating some EUV layers and avoiding the use of EUV double patterning altogether. This makes it slightly cheaper to produce, and in some cases it widens the process window and yield, although it comes at the cost of some transistor density.

N3P is on track for the second half of 2024.

Meanwhile, looking to the immediate future at TSMC, N3P has completed qualification and according to the company, its production performance is close to that of N3E. Due to optical shrinkage, N3P node processor developers are designed to increase performance by 4% at a single leak or reduce power consumption by up to 9% at the same clocks (prior design limits ~4% was between 10%). The new node is also set to increase transistor density by 4% for a 'mixed' chip design, which TSMC describes as a processor that includes 50% logic, 30% SRAM, and 20% analog circuits.











Promotion of PPA improvements of new process technologies

Data announced during conference calls, events, press briefings and press releases
TSMC
N3
Vs
N5
N3E
Vs
N5
N3P
Vs
N3E
N3X
Vs
N3P
power -25-30% -32% -5%~10% high
performance +10-15% +18% +5% +5%
Fmax @ 1.2V
Chip density ? ? 1.04x That's it
SRAM cell size 0.0199µm² (-5% vs N5) 0.021µm² (Same as N5) ? ?
Volume
Manufacturing
At the end of 2022 H2 2023 H2 2024 2025

While it looks like the original N3 (aka N3B) will have a relatively quiet lifecycle as Apple has been its only major customer, the N3E will be adopted by a wide range of TSMC customers, including many of the industry's biggest chips. Designers included.

Because N3P is an optical shrink of N3E, it is compatible with its predecessor in terms of IP blocks, process rules, electronic design automation (EDA) tools, and design methodologies. As a result, TSMC expects the majority of new tapouts to use N3P, not N3E or N3. This is logical because the N3P offers more performance than the N3E at a lower cost than the N3.

The most important aspect of N3P is that it's on track to be ready for production in the second half of this year, so expect chip designers to adopt it right away.

“We have also successfully delivered N3P technology,” said the TSMC executive. “It has passed qualification and production performance is close to N3E. (Process Technology) has also achieved product customer tap-out and will start production in the second half of this year. N3P's (PPA benefits ), we expect the majority of tap-outs on N3 to go to N3P.”

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