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Samsung Tapes Out Its First 3nm Smartphone SoC, Gets A Boost From Synopsys AI-Enabled Tools

Samsung Tapes Out Its First 3nm Smartphone SoC, Gets A Boost From Synopsys AI-Enabled Tools

This week, Samsung Electronics and Synopsys announced that Samsung has tapped its first mobile system-on-chip based on Samsung Foundry's 3nm gate-all-round (GAA) process technology. Announcement, coming from Electronic design automation Synopsys, further notes that Samsung used Synopsys.ai EDA Suite To accommodate the configuration and to verify the design of the SoC, which resulted in higher performance.

Samsung's unnamed high-performance mobile SoC 'flagship' relies on general-purpose CPU and GPU architectures, as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including Synopsys DSO.ai to refine designs and optimize yield, as well as Synopsys Fusion Compiler RTL-to-GDSII solutions for high performance, low power, and optimization. Area (PPA) to obtain.

And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is significant, there's another, even more important dimension to this announcement: It means that Samsung has finally tapped an advanced smartphone application processor onto its cutting edge. -edge 3nm GAAFET process.

Although Samsung Foundry is producing chips on its own GAA-equipped. SF3E (3 nm-class, 'initial' node) process for nearly two years, Samsung Electronics has never used this technology for its system-on-chips for smartphones or other complex devices. To date, SF3E has been used. Mainly for cryptocurrency mining ChipsProbably due to the inevitable early teething and production problems that came with the industry's first commercial GAAFET process.

For now, Samsung is not revealing which specific process node is being used for the SoC. The official Samsung/Synposys announcement only notes that it is for a GAA process node. With its first-generation 3nm-class SF3E, Samsung Foundry has quite a bit More advanced SF3 manufacturing technology which offers numerous improvements over the SF3E, and is slated for mass production in the coming quarters. Given the timing of the announcement, the reasonable bet is that they are using SF3.

As for Samsung's tooling partnership with Synopsys, the latter's tools are being credited with bringing some significant performance improvements to the chip design. Specifically, both firms are crediting these tools for improving the chip's peak clock speed to 300MHz while reducing dynamic power consumption by 10%. To accomplish this, Samsung Electronics' SoC developers used design partitioning optimization, multisource clock tree synthesis (MSCTS), and smart wire optimization to minimize signal interference. And using the Synopsys Fusion Compiler, they did all this while being able to skip weeks of 'manual' design work, according to a joint press release.

“Our long-standing collaboration has delivered leading-edge SoC designs,” said Kijun Hong, vice president of SLSI at Samsung Electronics. This is a significant milestone for successfully achieving the highest performance, power and area on the latest mobile CPU cores and SoC designs supported by Synopsys. state-of-the-art GAA process technologies, but through our partnership we have established a highly productive design system that continues to deliver impressive results.”

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