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PCIe 7.0 Draft 0.5 Spec Available: 512 GB/s over PCIe x16 On Track For 2025

PCIe 7.0 Draft 0.5 Spec Available: 512 GB/s over PCIe x16 On Track For 2025

The PCI-SIG released version 0.5 of the PCI-Express 7.0 specification to its members this week. This is the second draft of the specification and the final call for PCI-SIG members to submit their new features to the standard. The latest update on the development of the specification comes a few months after a year. PCI-SIG has published an early draft 0.3 specification.using the latest update with PCI-SIG reiterating that development of the new standard is on track for final release in 2025.

PCIe 7.0 is a next-generation interconnect technology for computers that is poised to deliver data transfer speeds of up to 128 GT/s per pin, double PCIe 6.0's 64 GT/s and quadruple PCIe 5.0's 32 GT/s. . This will allow a 16-lane (x16) connection to support 256 GB/sec bandwidth simultaneously in each direction, excluding encoding overhead. Such speeds will be useful for future data centers as well as artificial intelligence and high-performance computing applications that require high data transfer rates, including network data transfer rates.

To achieve its impressive data transfer rates, PCIe 7.0 doubles the bus frequency at the physical layer compared to PCIe 5.0 and 6.0. Otherwise, the standard retains the pulse amplitude modulation with four-level signaling (PAM4), 1b/1b FLIT mode encoding, and forward error correction (FEC) technologies already in use for PCIe 6.0. Otherwise, the PCI-SIG states that the PCIe 7.0 specifications focus on improved channel parameters and access, as well as improved power efficiency.

Overall, the engineers behind the standard have their work cut out for them, given that PCIe 7.0 requires doubling the bus frequency at the physical layer, a significant improvement over PCIe 6.0 with PAM4 signaling. retreated. Nothing comes for free when it comes to improving data signaling, and with PCIe 7.0, PCI-SIG is once again back to hard-mode development with the need to improve the physical layer – this time to 30GHz. To be walkable close to. However, how much of this heavy lifting will be accomplished by smart signaling (and timers) and how much will be accomplished by thorough material improvements, such as thicker printed circuit boards (PCBs) and low-loss materials, remains to be seen. Is.

The next major step for PCIe 7.0 is to finalize version 0.7 of the specification, which is considered a full draft, where all aspects must be fully defined, and the electrical specifications must be validated by test chips. After this iteration of the specification is released, no new features may be added. PCIe 6.0 ultimately went through 4 major drafts – 0.3, 0.5, 0.7, and 0.9 – before being finalized, so PCIe 7.0 is likely on the same track.

Once finalized in 2025, it should be a few years before the first PCIe 7.0 hardware hits shelves. Although development work on the controller IP and initial hardware is already underway, the process continues beyond the release of the final PCIe specification.

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