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JEDEC Extends DDR5 Memory Specification to 8800 MT/s, Adds Anti-Rowhammer Features

JEDEC Extends DDR5 Memory Specification to 8800 MT/s, Adds Anti-Rowhammer Features

When JEDEC released its DDR5 specification (JESD79) back in 2020, the standards-setting organization Exact specifications for modules with speed bins up to 6400 MT/s, while leaving the speculation open for further expansion with faster memory as technology advances. Now, a little more than three and a half years later, and the standards body and its members are gearing up to release a faster generation of DDR5 memory, housed in the newly updated JESD79-JC5 specification. The latest iteration of the DDR5 spec specifies official DDR timing up to 8800 MT/s, as well as adding some new features when it comes to security.

Diving in, the new specification outlines settings for memory chips (on all types of memory modules) with data transfer rates up to 8800 MT/s (AKA DDR5-8800). It turns out that all members of the JESD79 committee that set the specifications for DDR5—including memory chip manufacturers and memory controller designers—agree that DDR5-8800 is the DDR5 specification from a performance and cost standpoint. is a viable extension. Meanwhile, the addition of high-speed bins is possible through another JEDEC feature introduced in this latest specification, Self-Refresh Exit Clock Sync for I/O training optimization.




















JEDEC DDR5-A specification
Anandtech Data rate
MT/s
CAS Latency (Cycle) Absolute delay (ns) Peak BW
GB/s
DDR5-3200 Oh 3200 22 22 22 13.75 25.6
DDR5-3600 Oh 3600 26 26 26 14.44 28.8
DDR5-4000 Oh 4000 28 28 28 14 32
DDR5-4400 Oh 4400 32 32 32 14.55 35.2
DDR5-4800 Oh 4800 34 34 34 14.17 38.4
DDR5-5200 Oh 5200 38 38 38 14.62 41.6
DDR5-5600 Oh 5600 40 40 40 14.29 44.8
DDR5-6000 Oh 6000 42 42 42 14 48
DDR5-6400 Oh 6400 46 46 46 14.38 51.2
DDR5-6800 Oh 6800 48 48 48 14.12 54.4
DDR5-7200 Oh 7200 52 52 52 14.44 57.6
DDR5-7600 Oh 7600 54 54 54 14.21 60.8
DDR5-8000 Oh 8000 56 56 56 14 64.0
DDR5-8400 Oh 8400 60 60 60 14.29 67.2
DDR5-8800 Oh 8800 62 62 62 14.09 70.4

When it comes to the JEDEC standard for DDR5-8800, it specifies a relatively loose timing of CL62 62-62 for A-grade devices and CL78 77-77 for lower-end C-grade ICs. Unfortunately, the laws of physics governing DRAM cells haven't improved much over the past few years (or decades for that matter), so memory chips must still operate with similar absolute latencies, which should increase the CAS latency associated with 14ns remains the gold standard in this case, with CAS latencies at new speeds set to keep absolute latencies around that mark. But instead of systems willing to wait a little longer for results (in terms of cycles), the new specification improves peak memory bandwidth by up to 37.5%.

Of course, this is only the timing specified in the JEDEC specification, which is primarily of concern to server vendors. So we'll have to see how hard consumer memory manufacturers can make things for their XMP/EXPO-profiled memory. Extreme overclockers are already hitting such high speeds. 11,240 MT/s With the current generation of DRAM chips and CPUs, so the next generation may have a bit more headroom to play with.

Meanwhile, on the security front, the updated spec makes some changes that seem to be put in place to address the issue. Rowhammer style feats.. The big thing here is Per-Row Activation Counting (PRAC), which, as the name suggests, enables DDR5 to keep a count of how many times a row has been activated. Using this information, memory controllers can then determine if a memory queue has been activated excessively and is at risk of flipping bits, at which point they can refresh the queue correctly. and can roll back to re-consolidate the data.

Notably here, the JEDEC press release doesn't use the name rowhammer at any point (unfortunately, we haven't been able to look up the details ourselves). But based on the description alone, it's clearly intended to thwart Roheimer attacks, as they usually work by switching between refreshes a bit via a large number of activations.

Digging a little deeper, PRAC seems to be based on a recent Intel patent, Perfect row hammer tracking with multiple increments (US20220121398A1), which describes a very similar method called “perfect row hammer tracking” (PRHT). In particular, the Intel paper states that there is a performance cost associated with this technique because it increases overall queuing time. Ultimately, as the weakness underlying Rohmer is a matter of physics (cell density) rather than logic, it is not too surprising to see that any mitigation comes at a cost.

The updated DDR5 specification also drops support for Partial Array Self-Refresh (PASR) within the standard, citing security concerns. PASR is primarily aimed at power efficiency for initializing mobile memory, and as a refresh-related technology, likely overlaps somewhat with Rowhammer – even if it's a means of attacking memory. Be, or hinder the defense against Roheimer. Either way, with mobile devices increasingly moving to low-power optimized LPDDR technologies, PASR obsolescence doesn't immediately look like a major concern for consumer devices.

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