0
Intel Unveils PCIe “Thermal Throttling” In Linux Driver Update, Targeted At PCIe 6.0 & PCIe 7.0 Standards

Intel Unveils PCIe “Thermal Throttling” In Linux Driver Update, Targeted At PCIe 6.0 & PCIe 7.0 Standards

With PCIe standards seeing massive upgrades, temperature concerns are associated with the expected increased speed of migration to upcoming standards such as PCIe 6.0 and PCIe 7.0, but Intel has devised a unique solution.

To combat the high temperatures inside Next-Gen PCIe 6.0 and PCIe 7.0 links, Intel introduced a unique cooling mechanism that includes PCIe Throttle Control.

In a new Linux driver update, Intel has decided to address the temperature constraints associated with newer PCIe standards, such as PCIe Gen 6.0 and PCIe 7.0. Since it is not possible to install an active cooling solution on the PCIe interface itself, the latest driver update reduces the speed of the PCIe link in case of high temperatures. You can call this thermal throttling somewhat, but in this case, it's for PCIe lanes.

This series adds a PCIe bandwidth controller (bwctrl) and associated PCIe cooling driver to the thermal core side to limit PCIe link speed due to thermal reasons. The PCIe Bandwidth Controller is the PCI Express Bus Port service driver. A cooling device is created for each port that the service driver looks for if it supports variable speed.

This series only adds support for controlling PCIe link speed. Controlling PCIe Link Width can also be useful but AFAIK, there is no mechanism for this until PCIe 6.0 (L0p) so Link Width throttling is not covered by this series.

– Intel engineer Ilpo Järvinen

Image source: Kernel.org

The driver adds a “cooling device” to each PCIe link, allowing for speed manipulation. In situations where the temperature goes out of range, this device reduces the transfer speed for the corresponding PCIe link, ultimately ensuring functionality. It is important to note that this implementation is not associated with modern-day PCIe standards but is planned to be used for later standards, such as PCIe Gen 6.0, PCIe Gen 7.0, and beyond.

Well, this solution looks effective, but there may be performance concerns associated with it. However, we still have a long way to go before this technique is implemented. So, there is nothing to worry about for now. If the temperature issue persists at a wider level we may see some heat dissipation mechanism for the future PCIe interface as well as the hardware level.

Image Source: PCI-SIG

PCI-SIG recently unveiled the specification for PCIe 7.0. It is expected to launch by 2025 and should have market adoption by 2027-2028 (server first). The new standard is going to provide 512 GB/s bandwidth and 128 GT/s raw bit rate, double that of PCIe 6.0 and quadruple the rate of PCIe 5.0. As transfer speeds increase, we can expect new throttling mechanisms to be put in place to avoid overheating through these channels.

News Source: Phronics

Share this story.

Facebook

Twitter

About the Author

Leave a Reply