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AMD Strix & Strix Halo APU Official Docs Allegedly Leak: Up To 16 Zen 5 Cores, 40 RDNA 3+ iGPU, 60 AI TOPs, LPDDR5x-8000, 32 MB MALL

AMD Strix & Strix Halo APU Official Docs Allegedly Leak: Up To 16 Zen 5 Cores, 40 RDNA 3+ iGPU, 60 AI TOPs, LPDDR5x-8000, 32 MB MALL

An alleged “official” AMD document has leaked with information about AMD's Zen 5-powered Strix & Strix Halo APUs, spilling the beans on the full platform details for Red Team's next-gen mobility lineup. have gone

AMD Strix and Strix Halo APUs Mark a Major Update to the Ryzen Mobility Lineup: Featuring Zen 5 CPU, RDNA 3+ iGPU and XDNA 2 AI NPU Cores

Comes from the leak. HKEPC which was able to find the official AMD documentation posted on X by a user known as Izukias. The original post has been taken down but the tech outlet managed to get a good grasp of things and even shared the specs page for the Strix & Strix Halo lineup which will feature the next-gen Zen 5 CPU, RDNA 3+ iGPU and XDNA 2 NPU cores. Let's start with the complete details.

Image source: HKEPC

AMD Strix (1) APU specifications and platform specifications

First, we have the AMD Strix (Strix Point 1) family which will use the standard monolithic APU design. These chips will be built on the TSMC 4nm process node and will come in SKUs with up to 12 cores and 24 threads. We have seen several engineering prototypes leaked so far..

As far as cache is concerned, the APUs will adopt 12 MB of L2 cache (1 MB per core) and 24 MB of L3 cache which will be divided into 8 MB for Zen 5C and 16 MB for Zen 5 cores. The chips will also have an increase of 32 KB of L1 instruction cache and 48 KB of L1 data cache (32 KB on Zen 4). The APUs will offer 16 PCIe Gen 4 lanes.

As for memory support, the Ryzen Strix APUs will support LPDDR5-7500 and DDR5-5600 memory which is the standard case for most mainstream laptops. The next generation Ryzen AI-Engine is going to offer up to 50 TOPS (XDNA 2). AMD internally calls it AIE2+ or AI Engine 2 Plus.

On the iGPU side, we'll see a total of 8 RDNA 3+ WGPs or 16 compute units. We have seen this so far. The chip clocks up to 2.6 GHz in early prototypes So the final silicon could end up being around 3 GHz+. These APUs were once supposedly going to feature 16 MB of MALL cache.. All AMD Strix Point 1 APUs will be designed around the FP8 socket. It is reported that the Strix APU family will have TDPs between 45-65W which can be configured up to 28W.

AMD Ryzen 9050 Strix Mono Expected Features:

  • Zen 5 (4nm) monolithic design
  • Up to 12 cores in hybrid config (Zen 5 + Zen 5C)
  • 24 MB L3 cache / 12 MB L2 cache
  • 16 RDNA 3+ compute units
  • LPDDR5-7500/DDR5-5600 support
  • XDNA 2 engine integrated
  • Up to 50 AI tops
  • 16 PCIe Gen4 Lanes
  • 2H 2024 Launch (Expected)
  • FP8 Platform (28W-65W)

AMD Strix Halo APU specifications and platform details

AMD Strix Halo APUs will be chiplet offerings, using 3 dies, 2 CCDs and 1 IOD. The chips will feature up to 16 Zen 5 cores with 32 threads. These chips will maintain the same L1 and L2 cache structure to have a maximum of 16 MB of L2 cache while L3 cache will be increased to 32 MB per CCD. So we can see up to 64 MB of L3 cache on the above (two CCD) chips.

On the iGPU side, the Strix Halo APUs will retain the RDNA 3+ graphics architecture but will be equipped with 20 WGPs or 40 Compute Units. Additionally, to support such high-end iGPUs on a chiplet design, there will also be an additional 32 MB of MALL cache on the IOD that will eliminate bandwidth constraints for this uber iGPU.

Other specifications include support for up to LPDDR5x-8000 (256-bit) memory, and an AI “XDNA 2” NPU capable of delivering up to 60 TOPs. The Strix Halo APUs will be centered around the latest FP11 platforms. These APUs will feature TDPs of 70W (cTDP 55W) and support peak ratings of up to 130W.

AMD Ryzen 9050 Strix Halo Expected Features:

  • Zen 5 Chiplet Design
  • Up to 16 cores
  • 64 MB of shared L3 cache
  • 40 RDNA 3+ compute units
  • 32 MB RAM (for IGPU)
  • 256-bit LPDDR5X-8000 memory controller
  • XDNA 2 engine integrated
  • Up to 60 AI tops
  • 16 PCIe Gen4 Lanes
  • 2H 2024 Launch (Expected)
  • FP11 Platform (55W-130W)

For displays, AMD Strix and Strix Halo APUs have both eDP (DP2.1 HBR3) and external DP (DP2.1 UHBR10), USBC Alt-DP (DP2.1 UHBR10) and USB4 Alt-DP (DP2.1 UHBR10). Will come along. ) support as part of their media engines. Strix Halo DP2.1 will support up to UHBR20.

AMD is expected to launch its first Ryzen 9050 “Strix Point” APUs in the second half of this month so stay tuned for more information. Also expect more details at Computex 2024 during the AMD keynote..

AMD Ryzen Mobility CPUs:

CPU family name AMD sound wave? AMD Kraken Point AMD Fire Range AMD Strix Point Halo AMD Strix Point AMD Hawk Point AMD Dragon range AMD Phoenix AMD Rembrandt AMD Cezanne AMD Renoir AMD Picasso AMD Raven Ridge
Family branding TBD AMD Ryzen 9040 (H/U-Series) AMD Ryzen 8055 (HX-Series) AMD Ryzen 8050 (H-Series) AMD Ryzen 8050 (H/U-Series) AMD Ryzen 8040 (H/U-Series) AMD Ryzen 7045 (HX-Series) AMD Ryzen 7040 (H/U-Series) AMD Ryzen 6000
AMD Ryzen 7035
AMD Ryzen 5000 (H/U-Series) AMD Ryzen 4000 (H/U-Series) AMD Ryzen 3000 (H/U-Series) AMD Ryzen 2000 (H/U-Series)
Process node TBD 4nm 5 nm 4nm 4nm 4nm 5 nm 4 nm 6 nm 7 nm 7 nm 12 nm 14 nm
CPU core architecture Zen 6? Zen 5 Zen 5 Zen 5 + Zen 5C Zen 5 + Zen 5C Zen 4 + Zen 4C Zen 4 Zen 4 Zen 3+ Zen 3 Zen 2 Zen + Zen 1
CPU Cores/Threads (Maximum) TBD 8/16 16/32 16/32 12/24 8/16 16/32 8/16 8/16 8/16 8/16 4/8 4/8
L2 cache (max) TBD TBD TBD 24 MB 12 MB 4 MB 16 MB 4 MB 4 MB 4 MB 4 MB 2 MB 2 MB
L3 cache (max) TBD 32 MB TBD 64 MB 24 MB 16 MB 32 MB 16 MB 16 MB 16 MB 8 MB 4 MB 4 MB
Maximum CPU clocks TBD TBD TBD TBD TBD TBD 5.4 GHz 5.2 GHz 5.0 GHz (Ryzen 9 6980HX) 4.80 GHz (Ryzen 9 5980HX) 4.3 GHz (Ryzen 9 4900HS) 4.0 GHz (Ryzen 7 3750H) 3.8 GHz (Ryzen 7 2800H)
GPU core architecture RDNA 3+ iGPU RDNA 3+ 4nm iGPU RDNA 3+ 4nm iGPU RDNA 3+ 4nm iGPU RDNA 3+ 4nm iGPU RDNA 3 4nm iGPU RDNA 2 6nm iGPU RDNA 3 4nm iGPU RDNA 2 6nm iGPU Vega enhanced 7nm Vega enhanced 7nm Vega 14nm Vega 14nm
Maximum GPU cores TBD 12 CUs (786 cores) 2 CUs (128 cores) 40 CUs (2560 cores) 16 CUs (1024 cores) 12 CUs (786 cores) 2 CUs (128 cores) 12 CUs (786 cores) 12 CUs (786 cores) 8 CUs (512 cores) 8 CUs (512 cores) 10 CUs (640 cores) 11 CUs (704 cores)
Maximum GPU clocks TBD TBD TBD TBD TBD 2800 MHz 2200 MHz 2800 MHz 2400 MHz 2100 MHz 1750 MHz 1400 MHz 1300 MHz
TDP (cTDP down/up) TBD 15W-45W (65W cTDP) 55W-75W (65W cTDP) 55W-125W 15W-45W (65W cTDP) 15W-45W (65W cTDP) 55W-75W (65W cTDP) 15W-45W (65W cTDP) 15W-55W (65W cTDP) 15W -54W(54W cTDP) 15W-45W (65W cTDP) 12-35W (35W cTDP) 35W-45W (65W cTDP)
Launch. 2026? 2025? 2H 2024 2H 2024 2 AH 2024 Q1 2024 Q1 2023 Q2 2023 Q1 2022 Q1 2021 Q2 2020 Q1 2019 Q4 2018

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